1. Field of the Invention
The present invention generally relates to level detection technologies. In particular, the present invention relates to a three-level detector for differentiating the state of an input level pertaining to high level, low level, or floating but having no standby current.
2. Description of the Prior Art
Generally speaking, in the design of semiconductor integrated circuits some pins may be reserved testing or mode control applications. Some of those reserved pins are utilized to control test modes. While product costs are taken into account, three-level detectors are generally provided to differentiate the state of high level, low level, or floating at the reserved pins. Therefore, the number of the reserved pins provided for controlling test modes can be fewer than that of the desired test modes.
Referring to FIG. 1, the circuit diagram of a conventional three-level detector is schematically illustrated. Resistors R1 and R2 are connected between a power level V.sub.DD and a ground level GND in series. In the drawing, the node between the resistors R1 and R2 is designated as a node voltage V1. A level input 1 is used to receive a level signal, and electrically connected to the node between the resistors R1 and R1. Accordingly, the node voltage V1 is determined by the level signal, the power level V.sub.DD and the ground level GND as well.
Usually, the resistance of the resistor R1 is approximately equal to that of the resistor R2; therefore the node voltage V1 is half of the power level V.sub.DD when the level input 1 is floating. However, because of the limitation of the driving capacity as to the level input 1, the resistance of the resistors R1 and R2 should be cautiously chosen. If the resistance is too large, the circuit will be susceptible to noise interference. To the contrary, power consumption will be the problem while the chosen resistance is too small. Therefore, the resistance of the resistors R1 and R2 may range from about 10K to about 100K, preferably.
In FIG. 1, a pair of inverters N1 and N2 is provided to being configured with respective inputs connected to the node voltage V1, both outputs of which are connected to a decision logic circuit 10. Then, a detected result 2 is outputted by the decision logic circuit 10. Note that the threshold voltages of the inverters N1 and N2 are adjusted to be relatively-high and relatively-low, respectively. For instance, the inverter N1 has a threshold voltage between a level slightly lower than a high level voltage (e.g., the power level V.sub.DD) and half of the power level V.sub.DD. The inverter N2 has a threshold voltage between a level slightly higher than a low level voltage (e.g., the ground level GND) and half of the power level V.sub.DD. A detected result 2 standing for the state of the level input 1 is generated by the decision logic circuit 10. For example, the detected result 2 is comprised of two bits while three levels such as high, low, and floating are used to differentiation.
The operation of the level detector as shown in FIG. 1 will be described in the following. When a high level (e.g., 5V) is applied to the level input 1, the node voltage V1 will be powered to the same voltage as the high level. The node voltage V1 applies such a high level to the inputs of the inverters N1 and N2. Because the high level is greater than the relatively-high and relatively-low threshold voltages, both inverters N1 and N2 transmit low levels to the decision logic circuit 10, which generates the detected result 2 which indicates that the state of the level input 1 is high level. To the contrary, when a low level (e.g., 0V) is applied to the level input 1, the node voltage V1 will be powered to the same voltage as the low level. Therefore, the node voltage V1 applies such a low level to the inputs of the inverters N1 and N2. Because the low level is smaller than the relatively-high and relatively-low threshold voltages, both inverters N1 and N2 transmit high levels to the decision logic circuit 10, which generates the detected result 2 which indicates that the state of the level input 1 is low level. Moreover, if the level input 1 is floating, the node voltage V1 will be half of the power level V.sub.DD, and applied to the inputs of the inverters N1 and N2. Under these circumstances, inverters N1 and N2 transmit respectively a low level and a high level to the decision logic circuit 10, because the node voltage V1 is greater than the relatively-low threshold voltage but smaller than the relatively-high voltage. The detected result 2 indicating that the level input 1 is floating is thereafter generated by the decision logic circuit 10.
For decreasing the layout area required for the level detector, those resistors can be replaced by active devices. Referring to FIG. 2, the circuit diagram of another conventional level detector is schematically illustrated. In the drawing, two metal-oxide-semiconductor field-effect transistors (MOSFETs) M1 and M2 substitute for the resistors R1 and R2 as shown in FIG. 1, respectively. The P-type MOSFET M1 is configured with both its gate and drain tied to the node voltage V1, and its source connected to the power level V.sub.DD. However, the N-type MOSFET M2 is configured with both its gate and drain tied to the node voltage V1, and its source connected to the ground level GND.
In line with the trend of pursuing low power and portability, the quantity of power dissipated by each device within electronic products should be carefully taken into account. Nevertheless, there is a current flowing through the aforementioned level detectors no matter whether the state of the level input pertains to high level, low level, or floating. For the foregoing reason, there is a need for a level detector that can differentiate between input levels where the possible levels are high, low, or floating but having no standby current.